1. Field
Embodiments of the invention relate to electronics, and more particularly, to clock and data recovery systems.
2. Description of the Related Technology
Clock and data recovery (CDR) systems are employed in a variety of applications for recovering data from a high-speed serial data stream sent without a separate clock signal. CDR systems are typically used in, for example, telecommunications systems, optical networks, and chip-to-chip communication.
FIG. 1 is a schematic block diagram illustrating a conventional CDR system. The CDR system 10 includes a sampler 11 which samples data from a serial data stream 12 using a clock signal 13. The serial data stream 12 includes a string of serial data bits that transition at a data rate. At a given data rate, the serial data stream 12 has a unit interval (UI), or minimum time interval between transitions of the serial data stream. As data arrives in the serial data stream 12, the sampler 11 collects a data sample 14, a transition sample 15, a quarter UI sample 16, and a three-quarter UI sample 17. When the CDR system 10 is in a lock condition, the data sample 14 is taken approximately halfway into the UI of the data stream, so as to sample data furthest from the transition points. The transition sample 15 is taken from the beginning of the UI of the data stream during a lock condition, so as to sample the data stream near the points of transition. When the CDR system 10 is in a lock condition, the quarter UI sample 16 and three-quarter UI sample 17 are taken approximately a quarter into the UI and three-quarters into the UI, respectively, and are used for frequency detection.
With continuing reference to FIG. 1, the transition sample 15 and data sample 14 are provided to a phase detector 18, a coarse frequency detector 19, and a rotational frequency detector 20 on a bit-by-bit basis, when they are sampled by the sampler 11 from the serial data stream 12. For high-speed clock and data recovery, the phase and frequency detectors are typically custom circuits designed using a high-speed logic family, such as current mode logic (CML). The necessity of using CML or other high-speed logic families arises from the architectural constraint that the sample rate of the clock signal 13 matches the data rate of the serial data stream 12 during a lock condition. As the data rate of the serial data stream 12 increases, the rate at which samples are collected also increases, and therefore the phase detector 18, the rotational frequency detector 20 and the coarse frequency detector 19 operate at higher frequencies.
The phase and frequency detectors 18, 20, and 19 produce error signals 21 from the samples for use by a clock control block 22 in controlling an oscillator clock signal 26. A typical clock control block 22 includes a low-pass filter 24 and a voltage-controlled oscillator 25. As is well-known in the art, the low-pass filter 24 typically includes a charge pump, a resistor, and a capacitor, and has a filter transfer function selected for loop stability and transient performance. The error signals 21 can direct the charge pump to supply current pulses to the resistor and capacitor in the low-pass filter 24. The voltage-controlled oscillator 25 generates an oscillator clock signal 26 with a frequency which varies in relation to the filtered error signal coming from the low-pass filter 24.
Conventional CDR systems typically use a programmable divider 27 to match the sample rate to the data rate. For example, a VCO 26 that is limited by design to a frequency range of 1.7-3.4 GHz can lock to a rate of 100 Mbps by applying a 3.2 GHz clock signal to the programmable divider 27 with a programmable division rate set to 32. Similarly, the same CDR system locks to a rate of 1 Gbps by applying a 2.0 GHz clock signal to the programmable divider 27 with the programmable division rate set to 2. As a result of this division, the sample rate of the clock signal 13 matches the data rate of the serial data stream 12.